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H5PS1G63EFR
1Gb(64Mx16) DDR2 SDRAM
H5PS1G63EFR
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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/ Oct. 2008 1
H5PS1G63EFR
Revision History
Revision 0.1 Page All 5 0.2 61 0.3 0.4 1.0 64,67 56 62 56 1.1 69 History Initial data sheet released. -.500Mhz characteristics inserted. 500Mhz@2.0 Part Number deleted. IDD value(-25C) inserted. IDD testing parameters' value edited. Operating temperature condition changed. IDD Value(-20L) inserted. Thermal resistance value inserted. Typo corrected. (500Mhz tWR Value) Oct. 2008 Jul. 2008 Aug. 2008 Preliminary Preliminary Date May. 2008 Remark Preliminary
Jul. 2008
Preliminary
Aug. 2008
Note) The H5PS1G63EFR data sheet follows all of JEDEC DDR2 standard.
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Contents
1. Description
1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.2 Pin configuration 1.3 Pin Description
2. Functioanal Description
2.1 Simplified State Diagram 2.2 Basic Function & Operation of DDR2 SDRAM 2.2.1 Power up and Initialization 2.2.2 Programming the Mode and Extended Mode Registers 2.2.2.1 DDR2 SDRAM Mode Register Set(MRS) 2.2.2.2 DDR2 SDRAM Extended Mode Register Set 2.2.2.3 Off-Chip Driver(OCD) Impedance Adjustment 2.2.2.4 ODT(On Die Termination) 2.3 Bank Activate Command 2.4 Read and Write Command 2.4.1 Posted CAS 2.4.2 Burst Mode Operation 2.4.3 Burst Read Command 2.4.4 Burst Write Operation
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Write Data Mask
2.5 Precharge Operation 2.6 Auto Precharge Operation 2.7 Refresh Commands 2.7.1 Auto Refresh Command 2.7.2 Self Refresh Command 2.8 Power Down 2.9 Asynchronous CKE Low Event 2.10 No Operation Command 2.11 Deselect Command
3. Truth Tables 3.1 Command Truth Table
3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors 3.3 Data Mask Truth Table
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H5PS1G63EFR 4. Operation Conditions
4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Condition 4.3 Thermal Characteristics
5. AC & DC Operating Conditions
5.1 DC Operating Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 5.2 DC & AC Logic Input Levels 5.2.1 Input DC Logic Level 5.2.2 Input AC Logic Level 5.2.3 AC Input Test Conditions 5.2.4 Differential Input AC Logic Level 5.2.5 Differential AC Output Parameters 5.3 Output Buffer Levels 5.3.1 Output AC Test Conditions 5.3.2 Output DC Current Drive 5.3.3 OCD default characteristics
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5.4 IDD Specifications & Measurement Conditions 5.5 Input/Output Capacitance 5.6 Overshoot / Undershoot specification
6. Electrical Characteristics & AC Timing Specifications 7. Package Dimensions
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1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
* * * * * * * * * * * * *
VDD = 1.8 +/- 0.1V VDDQ = 1.8 +/- 0.1V All inputs and outputs are compatible with SSTL_18 interface 8 banks Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write(centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock * Programmable CAS latency 3,4, 5, 6 and 7 supported * Programmable additive latency 0, 1, 2, 3, 4 and 5 supported * Programmable burst length 4/8 with both nibble sequential and interleave mode * Internal eight bank operations with single pulsed RAS * Auto refresh and self refresh supported * tRAS lockout supported * 8K refresh cycles /64ms * JEDEC standard 84ball FBGA(x16) * Full strength driver option controlled by EMR * On Die Termination supported www..com Chip Driver Impedance Adjustment supported * Off * Read Data Strobe supported (x8 only) * Self-Refresh High Temperature Entry * Average Refresh Period 7.8us at lower than Tcase 85C, 3.9us at 85C1.1.2 Ordering Information
Part No. H5PS1G63EFR-20L H5PS1G63EFR-25C VDD/VDDQ=1.8V Power Supply Clock Frequency 500Mhz 400Mhz Max Data Rate 1000Mbps/pin 800Mbps/pin Interface Package
SSTL_18
84Ball FBGA
Note) Above Hynix P/N's are Lead-free, RoHS Compliant and Halogen-free.
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1.2 Pin configuration
64Mx16 DDR2 PIN CONFIGURATION(Top view: see balls through package)
1
2
3
7
8
9
VDD DQ14 VDDQ DQ12 VDD DQ6 VDDQ DQ4 VDDL
NC VSSQ DQ9 VSSQ NC VSSQ DQ1 VSSQ VREF CKE
VSS UDM VDDQ DQ11 VSS LDM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC, A14
A B C D E F G H J K L M N P R
VSSQ UDQS VDDQ DQ10 VSSQ LDQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC, A15
UDQS VSSQ DQ8 VSSQ LDQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 NC, A13
VDDQ DQ15 VDDQ DQ13 VDDQ DQ7 VDDQ DQ5 VDD ODT
NC, BA2
BA0 A10/AP
VDD
VSS
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A3 A7
VSS
VDD
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS # of Bank Bank Address Auto Precharge Flag Row Address Column Address Page size 64Mx16 8 BA0, BA1, BA2 A10/AP A0 - A12 A0-A9 2 KB
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1.3 PIN DESCRIPTION
PIN CK, CK TYPE Input DESCRIPTION Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained HIGH throughout READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. Chip Select : Enables or disables all inputs except CK, CK, CKE, DQS and DM. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal to the DDR2 SDRAM. When enabled, ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode Register(EMR(1)) is programmed to disable ODT. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. Bank Address Inputs : BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied(For 2Mb and 512Mb, BA2 is not applied). Bank address also determines if one of the mode register or extended mode register is to be accessed during a MR or EMR command cycle. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code during MRS or EMRS commands. Data input / output : Bi-directional data bus Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. The data strobes LDQS & UDQS may be used in single ended mode or paired with optional complementary signals LDQS & UDQS to provide differential pair signaling to the system during both reads and wirtes. An EMR(1) control bit enables or disables all complementary data strobe signals. In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMR(1) x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMR(1) x16 LDQS and UDQS No Connect : No internal electrical connection is present. Supply Supply Supply Supply Supply Supply Supply DQ Power Supply : 1.8V +/- 0.1V DQ Ground DLL Power Supply : 1.8V +/- 0.1V DLL Ground Power Supply : 1.8V +/- 0.1V Ground Reference voltage. 7
CKE
Input
CS
Input
ODT RAS, CAS, WE DM (LDM, UDM)
Input Input Input
BA0 - BA2
Input
A0 -A12
Input
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DQ Input/Output
(UDQS),(UDQS) (LDQS),(LDQS)
Input/Output
NC VDDQ VSSQ VDDL VSSDL VDD VSS VREF Rev. 1.1/ Oct. 2008
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2. Functional Description
2.1 Simplified State Diagram
Initialization Sequence CKEL OCD calibration SRF PR Setting MRS EMRS Idle MRS All banks precharged CKEL ACT CKEH Precharge Power Down CKEL REF Refreshing CKEH
Self Refreshing
CKEL CKEL Active Power Down CKEL
Activating
CKEL Automatic Sequence Command Sequence
CKEH Bank Active
Write
Write WRA Writing RDA Read
Read Read
Reading
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WRA RDA Writing with Autoprecharge PR, PRA PR, PRA PR, PRA Reading with Autoprecharge RDA
Precharging
CKEL = CKE low, enter Power Down CKEH = CKE high, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured in full detail.
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2.2 Basic Function & Operation of DDR2 SDRAM
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
2.2.1 Power up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95 V max, AND - Vref tracks VDDQ/2. or - Apply VDD before or at the same time as VDDL. - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref.
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at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition. 3. For the minimum of 200 us after stable power and clock(CK, CK), then apply NOP or deselect & take CKE high. 4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "Low" to BA0, "High" to BA1.)*2 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "High" to BA0 and BA1.)*2 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1.) 8. Issue a Mode Register Set command for "DLL reset". (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1.) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ). If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of
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EMRS. 13. The DDR2 SDRAM is now ready for nomal operation. *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. *2) Sequence 5 and 6 may be performed between 8 and 9.
Initialization Sequence after Power Up
tCH tCL
CK /CK
tIS
CKE ODT Command
NOP PRE ALL 400ns tRP EMRS MRS PRE ALL tMRD tRP REF REF tRFC MRS EMRS EMRS ANY CMD
tMRD
tRFC
tMRD
Follow OCD Flowchart OCD Default
tOIT
DLL ENABLE
DLL RESET
min. 200 Cycle OCD CAL. MODE EXIT
2.2.2 Programming the Mode and Extended Mode Registers
For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be www..com programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents.
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H5PS1G63EFR 2.2.2.1 DDR2 SDRAM Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn't support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 ~ A11. Refer to the table for specific codes. Address Field
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Extended Mode Register
0
0
0
PD
WR
DLL
TM
/CAS Latency
BT
Burst Length
A8 0 1
DLL Reset No Yes
A7 0 1
mode Normal Test
A3 0 1
Burst Type Sequential Interleave
Burst Length A2 0 0 A1 1 1 A0 0 1 BL 4 8
A12 0
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Active power down exit time Fast exit(use tXARD) Slow exit(use tXARDS)
BA0
Write recovery for autoprecharge A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WR(cycles)*1 Reserved 2 3 4 5 6 7 Reserved
CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved Reserved 3 4 5 6 7
BA1
MRS mode MRS EMRS(1) EMRS(2) EMRS(3): Reserved
0 0 1 1
0 1 0 1
MRS Default setting Active Power donw exit Fast Exit WR WR=4 /CAS Latency CL=4 BT Seq. Burst Length BL=4
*1: WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
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2.2.2.2 DDR2 SDRAM Extended Mode Register Set
EMRS(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended mode register(1) is not defined, therefore the extended mode register(1) must be written after power-up for proper operation. The extended mode register(1) is written by asserting low on CS, RAS, CAS, WE, high on BA0 and low on BA1, while controlling the states of address pins A0 ~ A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3~A5 determines the additive latency, A7~A9 are used for OCD control, A10 is used for DQS disable. A2 and A6 are used for ODT setting.
DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
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EMRS(1) Programming Address Field
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Extended Mode Register
0
0
1
Qoff
0
/DQS
OCD Program
Rtt
Additive latency
Rtt
D.I.C
DLL
BA1
BA0
MRS mode MRS EMRS(1) EMRS(2) EMRS(3): Reserved
A6 0 0 1 1
A2 0 1 0 1
Rtt (NOMINAL) ODT Disabled 75 ohm 150 ohm 50 ohm A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1
A0 0 1
DLL Enable Enable Disable
0 0 1 1
0 1 0 1
A3 0 1 0 1 0 1 0 1
Additive Latency
0 1 2 3 4 5 6 Reserved
A9 0 0 0 1 1
A8 0 0 1 0 1
A7 0 1 0 0 1
OCD Calibration Program OCD Calibration mode exit; maintain setting Drive(1) Drive(0) Adjust modea OCD Calibration default b
a: When Adjust mode is issued, AL from previously set value must be applied. b: After setting to default, OCD mode needs to be exited by setting A9-A7 to 000. Refer to the following 2.2.2.3 section for detailed information
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A12 0 1
Qoff Output buffer enabled Output buffer disabled A10 (/DQS Enable) 0(Enable) 1(Disable) Strobe Function Matrix DQS DQS DQS /DQS /DQS Hi-z
A10 0 1
DQS Enable Disable
A1 0 1
Output Driver Impedence Control Normal Weak
Driver Size 100% 60%
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H5PS1G63EFR EMR(2)
The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) must be programmed during initialization for proper operation. The extended mode register(2) is written by asserting LOW on /CS,/RAS,/CAS,/WE, HIGH on BA1 and LOW on BA0, while controling the states of address pins A0~A15. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register(2). The mode register set command cycle time(tMRD) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. EMR(2) Programming:
BA2 BA1 BA0 A15 ~ A13 0*1 1
A12
A11 0*1
A10
A9
A8
A7
A6
A5 0*1
A4
A3
A2
A1 PASR*3
A0
Address Field Extended Mode Register(2)
0
SRF
DCC*3
A7 0 1 BA1 0 0 1 1 A2
0 0
High Temp Self-refresh Rate Enable Disable Enable(Optional)*2
BA0 0 1 0 1 A1
0 0
MR mode MR EMR(1) EMR(2) EMR(3):Reserved A0
0 1 0 1 0 1 0 1
A3 0 1
DCC Enable(Optional)*4 Disable Enable
Partial Array Self Refresh for 8 banks
Full Array Half Array (BA[2:0]=000,001,010&011) Quarter Array (BA[2:0]=000&001) 1/8th Array (BA[2:0]=000) 3/4 Array (BA[2:0]=010,011,100,101,110&111) Half Array (BA[2:0]=100,101,110&111) Quarter Array (BA[2:0]=110&111) 1/8th Array (BA[2:0]=111)
Partial Array Self Refresh for 4 banks
Full Array Half Array (BA[1:0]=00&01) Quarter Array (BA[1:0]=00) Not Defined 3/4 Array (BA[1:0]=01,10&11) Half Array (BA[1:0]=10&11) Quarter Array (BA[1:0]=11) Not Defined
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*1 : The rest bits in EMR(2) are reserved for future use and all bits except A7, BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. *2 : Currently the periodic Self-Refresh interval is hard coded whithin the DRAM to a specific value. EMR(2) bit A7 is a migration plan to support higher Self-Refresh entry. However, since this Self-Refresh control function is an option and to be phased-in by manufacturer individually, checking on the DRAM parts for function availablity is necessary. For more details, please refer to "Operating Temperature Condition" section at "Chapter 5. AC & DC operation conditions". *3 Optional in DDR2 SDRAM. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. If the PASR feature is not supported, EMR(2)[A0-A2] must be set to 000 when programming EMR(2). *4 Optional in DDR2 SDRAM. JEDEC standard DDR2 SDRAM may or may not have DCC (Duty Cycle Corrector) implemented, and in some of the DRAMs implementing DCC, user may be given the controllability of DCC thru EMR(2)[A3] bit. JEDEC standard DDR2 SDRAM users can look at manufacturer's data sheet to check if the DRAM part supports DCC controllability. If Optional DCC Controllability is supported, user may enable or disable the DCC by programming EMR(2)[A3] accordingly. If the controllability feature is not supported, EMR(2)[A3] must be set to 0 when programming EMR(2). Rev. 1.1/ Oct. 2008 14
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EMR(3)
No function is defined in extended mode register(3). The default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during initialization for proper operation. EMR(3) Programming:
BA2 BA1 BA0 A15 ~ A13 0*1 1
A12
A11
A10
A9
A8 0*1
A7
A6
A5
A4
A3
A2
A1
A0
Address Field Extended Mode Register(2)
1
*1 :All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during initialization.
Figure 6. EMR(3) programming
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H5PS1G63EFR 2.2.2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termiantion) should be carefully controlled depending on system environment. MRS shoud be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit
EMRS: Drive(1) DQ & DQS High; DQS Low
EMRS: Drive(0) DQ & DQS Low; DQS High
ALL OK Test Need Calibration EMRS: OCD calibration mode exit
ALL OK Test Need Calibration EMRS: OCD calibration mode exit
EMRS : Enter Adjust Mode
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EMRS : Enter Adjust Mode
BL=4 code input to all DQs Inc, Dec, or NOP
BL=4 code input to all DQs Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
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H5PS1G63EFR Extended Mode Register Set for OCD impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM. In Drive(1) mode, all DQ, DQS signals are driven high and all DQS signals are driven low. In drive(0) mode, all DQ, DQS signals are driven low and all DQS signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in Table x. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in order to maintain the default or calibrated value.
Off- Chip-Driver program
A9 0 0 0 1 1
A8 0 0 1 0 1
A7 0 1 0 0 1
Operation OCD calibration mode exit Drive(1) DQ, DQS high and DQS low Drive(0) DQ, DQS low and DQS high Adjust mode OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to DDR2 SDRAM as in table X. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in table X means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may www..com be any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must be applied
Table X : Off- Chip-Driver Program
4bit burst code inputs to all DQs DT0 0 0 0 0 1 0 0 1 1 DT1 0 0 0 1 0 1 1 0 0 DT2 0 0 1 0 0 0 1 0 1 DT3 0 1 0 0 0 1 0 1 0 Pull-up driver strength NOP (No operation) Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step Reserved
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Other Combinations
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For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by MRS addressing mode (ie. sequential or interleave).
OCD adjust mode OCD calibration mode exit NOP NOP NOP NOP NOP
CMD CK CK
EMRS
EMRS
NOP
WL
DQS
WR
DQS_in
tDS tDH DT0
DQ_in DM Drive Mode
DT1
DT2
DT3
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram.
Enter Drive mode OCD calibration mode exit NOP NOP NOP EMRS
CMD www..comEMRS CK CK DQS DQS DQ
tOIT Hi-Z
Hi-Z DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0) DQs high for Drive(1) DQs low for Drive(0)
tOIT
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On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes. ODT is turned off and not supported in SELF REFRESH mode.
FUNCTIONAL REPRESENTATION OF ODT
VDDQ sw1
Rval1
VDDQ sw2
Rval2
DRAM Input Buffer
Rval1 Rval2
Input Pin
sw1 VSSQ
sw2 VSSQ
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Switch sw1 or sw2 is enabled by ODT pin. Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS Termination included on all DQs, DM, DQS, DQS pins. Target Rtt (ohm) = (Rval1) / 2 or (Rval2) / 2
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H5PS1G63EFR ODT timing for active/standby mode
T0
CK CK
T1
T2
T3
T4
T5
T6
CKE
tIS
ODT
tIS
tAOND
Internal Term Res.
tAOFD
RTT
tAON,min
tAOF,min tAON,max
tAOF,max
ODT timing for powerdown mode
T0
CK CK
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T1
T2
T3
T4
T5
T6
CKE
tIS
ODT
tIS
tAOFPD,max tAOFPD,min
Internal Term Res.
RTT
tAONPD,min tAONPD,max
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T-5 CK CK
T-4
T-3
T-2
T-1
T0
T1
T2
T3
T4
tANPD tIS
CKE
Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode.
tIS ODT tAOFD Internal Term Res. tIS ODT tAOFPDmax Internal Term Res. tIS
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RTT
Active & Standby mode timings to be applied.
RTT
Power Down mode timings to be applied.
tAOND Internal Term Res. tIS ODT tAONPDmax Internal Term Res. RTT RTT
Active & Standby mode timings to be applied.
Power Down mode timings to be applied.
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T0 CK CK tIS CKE tAXPD T1 T4 T5 T6 T7 T8 T9 T10 T11
Exiting from Slow Active Power Down Mode or Precharge Power Down Mode.
tIS
Active & Standby mode timings to be applied.
ODT tAOFD Internal Term Res. tIS RTT
Power Down mode timings to be applied.
ODT tAOFPDmax Internal Term Res. RTT tIS
Active & Standby www..com timings to mode be applied.
ODT tAOND Internal Term Res. tIS RTT
Power Down mode timings to be applied.
ODT tAONPDmax Internal
Term Res.
RTT
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2.3 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock. The bank addresses BA0 ~ BA2 are used to select the desired bank. The row address A0 through A15 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate commands is tRRD. In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the number of sequential ACT commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are as follows: * 8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW[ns] by tCK[ns] or tCK(avg)[ns], depending on the speed bin, and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) or (tFAW/tCK(avg) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued at or betwen clock N+1 through N+9. * 8 bank device Precharge All Allowance : tRP for a Precharge All command for an 8 Bank device will equal to tRP+1*tCK or tnRP + 1*nCK, depending on the speed bin, where tnRP=tRP/tCK(avg) rounded up to the next interger, where tRP is the value for a single bank pre-charge.
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T0 CK / CK
T1
T2
T3
Tn
..........
Tn+1
Tn+2
Tn+3
Internal RAS-CAS delay (>= tRCDmin)
ADDRESS
Bank A Row Addr.
Bank A Col. Addr.
tRCD =1
Bank B Bank B Col. Addr. Row Addr. CAS-CAS delay time (tCCD) additive latency delay (AL)
Bank A .......... Addr.
Bank B Addr.
Bank A Row Addr.
Read Begins
RAS - RAS delay time (>= tRRD) Bank A Activate
Bank A Post CAS Read
COMMAND
: "H" or "L"
Bank B Activate
Bank B Post CAS Read
. . . . . . . . Bank A .. Precharge
Bank B Precharge
Bank A Activate
Bank Active (>= tRAS) RAS Cycle time (>= tRC)
Bank Precharge time (>= tRP)
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
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2.4 Read and Write Command
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles.
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2.4.1 Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in Read burst and Wirte burst section)
Examples of posted CAS operation
Example 1 Read followed by a write to the same bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
-1 CK/CK
0
1
2
3
4
5
6
7
8
9
10
11
12
CMD DQS/DQS DQ
Active A-Bank
Read A-Bank
Write A-Bank
WL = RL -1 = 4
AL = 2 > = tRCD
CL = 3 RL = AL + CL = 5
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
> = tRAC
Example 2 Read followed by a write to the same bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
-1
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0
1
2
3
4
5
6
7
8
9
10
11
12
CK/CK AL = 0 CMD DQS/DQS DQ
Active A-Bank Read A-Bank Write A-Bank
CL = 3 > = tRCD
WL = RL -1 = 2
RL = AL + CL = 3
Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3
> = tRAC
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2.4.2 Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop command is not supported on DDR2 SDRAM devices.
Burst Length and Sequence
Burst Length Starting Address (A2 A1 A0) 000 001 4 010 011 000 001 010 011 8 100 101 110 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 Sequential Addressing (decimal) 0, 1, 2, 3 1, 2, 3, 0 Interleave Addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2
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111
Note: Page length is a function of I/O organization and column addressing
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2.4.3 Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set (1)(EMRS(1)). DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation.
tCH CK tCL
CK
CK
DQS
DQS/DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
DQ
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Figure YY-- Data output (read) timing
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Posted CAS READ A
NOP
NOP
NOP
NOP
NOP =< tDQSCK
NOP
NOP
NOP
DQS/DQS
AL = 2 RL = 5 CL =3
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
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Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8)
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
READ A
NOP
NOP
NOP =< tDQSCK
NOP
NOP
NOP
NOP
NOP
DQS/DQS
CL =3 RL = 3
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4
T0 CK/CK T1 Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5
CMD
Post CAS READ A
NOP
NOP
Post CAS NOP WRITE A tRTW (Read to Write turn around time)
NOP
NOP
NOP
NOP
DQS/DQS
RL =5
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WL = RL - 1 = 4
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DIN A0
DIN A1
DIN A2
DIN A3
The minimum time from the burst read command to the burst write command is defined by a read-to-writeturn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
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Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL = 4
T0 CK/CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS READ A
NOP
Post CAS READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
AL = 2 RL = 5 CL =3
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT B0
DOUT B1
DOUT B2
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
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Reads interrupted by a read
Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed.
Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8)
CK/CK
CMD
Read A
NOP
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note
1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited. 3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto Precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another Read with Auto Precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced www..com burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst to actual length set in the mode register and not the actual burst (which is shorter because of interrupt).
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2.4.4 Burst Write Operation
The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR). DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation.
tDQSH tDQSL
DQS
DQS/ DQS
DQS tWPRE tWPST
DQ
tDS
D
D
D tDH DMin
D tDH DMin
tDS DMin
DM
DMin
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Data input (write) timing
Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 Tn
CMD
Posted CAS WRITE A
NOP
NOP < = tDQSS
NOP
NOP
NOP
NOP
NOP
Precharge
Completion of the Burst Write
DQS/DQS
WL = RL - 1 = 4 > = WR DIN A0 DIN A1 DIN A2 DIN A3
DQs
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Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 Tn
CMD
WRITE A
NOP
NOP < = tDQSS
NOP
NOP
NOP
Precharge
NOP
Bank A Activate
Completion of the Burst Write
DQS/ DQS
WL = RL - 1 = 2 > = WR DIN A0 DIN A1 DIN A2 DIN A3 > = tRP
DQs
Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
T0 CK/CK
Write to Read = CL - 1 + BL/2 + tWTR Post CAS READ A
T1
T2
T3
T4
T5
T6
T7
T8
T9
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
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DQS DQS
WL = RL - 1 = 4 AL = 2 RL =5 > = tWTR CL = 3
DQS/ DQS
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DOUT A0
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
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Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
T0 CK/CK
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS Write A
NOP
Post CAS Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/ DQS
WL = RL - 1 = 4
DQS DQS
DQ's
DIN A0
DIN A1
DIN A2
DIN A3
DIN B0
DIN B1
DIN B2
DIN B3
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated
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Writes interrupted by a write
Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not allowed.
Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK/CK
CMD
NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Notes: 1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto Precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowed by another Write with Auto Precharge command. www..com 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
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2.4.5 Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit organization is not used during read cycles.
Data Mask Timing DQS/ DQS DQ
DM tDS tDH tDS tDH
Data Mask Function, WL=3, AL=0, BL = 4 shown Case 1 : min tDQSS
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Write
tDQSS
tWR
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2.5 Precharge Operation
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are LOW and CAS is HIGH at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 for 512Mb and four address bits A10, BA0~BA2 for 1Gb and higher densities are used to define which bank to precharge when the command is issued. For 8 bank devices, refer to Bank Active section of this data sheet.
Bank Selection for Precharge by Address Bits
A10 LOW LOW LOW LOW LOW LOW LOW LOW HIGH BA2 LOW LOW LOW LOW HIGH HIGH HIGH HIGH DON'T CARE BA1 LOW LOW HIGH HIGH LOW LOW HIGH HIGH DON'T CARE BA0 LOW HIGH LOW HIGH LOW HIGH LOW HIGH DON'T CARE Precharged Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7only All Banks 1Gb and higher 1Gb and higher 1Gb and higher 1Gb and higher Remarks
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Burst Read Operation Followed by Precharge
Minium Read to precharge command spacing to the same bank = AL + BL/2 clocks For the earliest possible precharge, the precharge command may be issued on the rising edge which is "Additive latency(AL) + BL/2 clocks" after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock egde that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.
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Example 1: Burst Read Operation Followed by Precharge: RL = 4, AL = 1, CL = 3, BL = 4, tRTP <= 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
NOP AL + BL/2 clks
NOP
Precharge
NOP
NOP
NOP
Bank A Active
NOP
DQS/DQS
AL = 1 RL =4 CL = 3 > = tRP
DQ's
> = tRAS > = tRTP
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CL =3
Example 2: Burst Read Operation Followed by Precharge: RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
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AL + BL/2 clks
DQS/DQS
AL = 1 RL =4 CL = 3
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
> = tRTP first 4-bit prefetch second 4-bit prefetch
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Example 3: Burst Read Operation Followed by Precharge: RL = 5, AL = 2, CL = 3, BL = 4, tRTP <= 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Posted CAS READ A
NOP
NOP AL + BL/2 clks
NOP
Precharge A
NOP
NOP
Bank A Activate
NOP
DQS/DQS
> = tRP AL = 2 RL =5 CL =3
DQ's
> = tRAS > = tRTP
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CL =3
Example 4: Burst Read Operation Followed by Precharge: RL = 6, AL = 2, CL = 4, BL = 4, tRTP <= 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
NOP
NOP AL + BL/2 Clks
NOP
Precharge A
NOP
NOP
Bank A Activate
NOP
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DQS/DQS
> = tRP AL = 2 RL = 6 CL =4
DQ's
> = tRAS > = tRTP CL =4
DOUT A0
DOUT A1
DOUT A2
DOUT A3
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Example 5: Burst Read Operation Followed by Precharge: RL = 4, AL = 0, CL = 4, BL = 8, tRTP > 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
Bank A Activate
AL + 2 Clks + max{tRTP;2 tCK}*
DQS/DQS
AL = 0 CL =4 RL = 4 > = tRP
DQ's
> = tRAS > = tRTP first 4-bit prefetch * : rounded to next interger second 4-bit prefetch
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
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H5PS1G63EFR Burst Write followed by Precharge
Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.
Example 1: Burst Write followed by Precharge: WL = (RL-1) =3
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
Completion of the Burst Write
> = WR
DQS/DQS
WL = 3
DQs
DIN A0
DIN A1
DIN A2
DIN A3
Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T9
CMD
Posted CAS WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
Completion of the Burst Write
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> = tWR
DQS/DQS
WL = 4
DQs
DIN A0
DIN A1
DIN A2
DIN A3
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2.6 Auto Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the auto-precharge function. When a Read or a Write command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the READ or WRITE command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst. Auto-precharge is also implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the auto precharge command may be issued with any read or write command.
Burst Read with Auto Precharge
If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) www..com is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + (tRTP + tRP)*, where "*" means: "rounded up to the next integer". In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
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H5PS1G63EFR Example 1: Burst Read Operation with Auto Precharge: RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS
READ A Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP > = tRP
NOP
Bank A Activate
AL + BL/2 clks
DQS/DQS
AL = 1 RL =4 CL = 3
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
> = tRTP first 4-bit prefetch second 4-bit prefetch tRTP Precharge begins here
Example 2: Burst Read Operation with Auto Precharge: RL = 4, AL = 1, CL = 3, BL = 4, tRTP > 2 clocks
T0 CK/CK T1 T2 T3 T4 T5 T6 T7 T8
CMD
Post CAS READ A
Autoprecharge
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Activate
NOP
> = AL + tRTP + tRP
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DQS/DQS
AL = 1 RL =4 CL = 3
DQ's
DOUT A0
DOUT A1
DOUT A2
DOUT A3
4-bit prefetch tRTP Precharge begins here tRP
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Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank(tRC Limit):
RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
T0 CK/CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
CMD
Post CAS READ A
NOP
NOP > = tRAS(min)
NOP
NOP
NOP
NOP
NOP
Bank A Activate
Auto Precharge Begins
DQS/DQS
AL = 2 RL = 5
> = tRP
CL =3 DOUT A0 DOUT A1 DOUT A2 DOUT A3
DQ's
> = tRC
CL =3
Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same Bank(tRP Limit):
RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks)
T0 CK/CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
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CMD
READ A
NOP
NOP
NOP
NOP
NOP
NOP
Bank A Activate
NOP
> = tRAS(min)
Auto Precharge Begins
DQS/DQS
AL = 2 RL = 5
> = tRP
CL =3 DOUT A0 DOUT A1 DOUT A2 DOUT A3
DQ's
> = tRC
CL =3
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Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, BL = 4, tRP=3
T0 CK/CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
Tm
CMD
Post CAS WRA BankA
NOP
NOP
NOP
NOP
NOP
NOP Auto Precharge Begins
NOP
Bank A Active
Completion of the Burst Write
DQS/DQS
WL =RL - 1 = 2
> = WR
DIN A1 DIN A2 DIN A3
> = tRP
DQs
DIN A0
> = tRC
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Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, BL = 4, tRP=3
T0 CK/CK
A10 = 1 Post CAS CMD WRA Bank A NOP NOP NOP NOP NOP NOP Auto Precharge Begins NOP Bank A Active
T3
T4
T5
T6
T7
T8
T9
T12
Completion of the Burst Write
DQS/DQS
WL =RL - 1 = 4
> = WR
DIN A1 DIN A2 DIN A3
> = tRP
DQs
DIN A0
> = tRC
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2.7 Refresh Commands
DDR2 SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an explicit Auto-Refresh command, or by an internally timed event in SELF REFRESH mode. Dividing the number of device rows into the rolling 64ms interval, tREFI, which is a guideline to controllers for distributed refresh timing. For example, a 512Mb DDR2 SDRAM has 8192 rows resulting in a tREFI of 7.8 . To avoid excessive interruptions to the memory controller, higher density DDR2 SDRAMS maintain 7.8 average refresh time and perform multiple internal refresh bursts. In these cases, the refresh recovery times, tRFC an tXSNR are extended to accomodate these internal operations.
2.7.1 Auto Refresh Command
AUTO REFRESH is used during normal operation of the DDR2 SDRAM. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater than or equal to the Refresh cycle time (tRFC). To allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 * tREFI.
T0 CK/CK
High
T1
T2
T3
Tm
Tn
Tn + 1
CKE
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> = tRP
> = tRFC
> = tRFC
CMD
Precharge
NOP
NOP
REF
REF
NOP
ANY
2.7.2 Self Refresh Operation
The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the Self Refresh mod, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon existing Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are "don't care". The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode.The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self Refresh operation.
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The procedure for existing Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires.NOP or deselect commands must be registered on each positive clock edge during the Self Refresh exit interval. ODT should also be turned off during tXSRD. The Use of Self Refresh mode introduce the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
T0 T1 T2 T3 T4 T5 T6 Tm Tn
tCK tCH tCL
CK CK
> = tXSNR tRP* > = tXSRD
CKE
tIS tAOFD
ODT
tIS
tIS tIS tIH
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CMD
Self Refresh
NOP
NOP
NOP
Valid
- Device must be in the "All banks idle" state prior to entering Self Refresh mode. - ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied. - tXSRD is applied for a Read or a Read with autoprecharge command - tXSNR is applied for any command except a Read or a Read with autoprecharge command.
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2.8 Power-Down
Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are "Don't Care". CKE low must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of this data sheet.
Basic Power Down Entry and Exit timing diagram
CK/CK
tIS CKE VALID tCKE NOP tCKE NOP VALID tXP, tXARD, tXARDS tCKE Exit Power-Down mode Don't Care VALID VALID tIH tIS tIH tIH tIS tIH tIS tIH
Command
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Enter Power-Down mode
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Read to power down entry
T0 CK CK CMD CKE DQ DQS DQS T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
AL + CL Q Q Q Q RD BL=4
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Read operation starts with a read command and CKE should be kept high until the end of burst operation.
CMD CKE DQ DQS DQS
RD BL=8
CKE should be kept high until the end of burst operation.
AL + CL Q Q Q Q Q Q Q Q
Read with Autoprecharge to power down entry
T0 CK CK CMD
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RDA BL=4 PRE AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied AL + CL
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CKE DQ DQS DQS T0 T1 T2
CKE should be kept high until the end of burst operation.
Q
Q
Q
Q
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Start internal precharge CMD CKE
AL + CL RDA BL=8 AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied PRE
CKE should be kept high until the end of burst operation.
DQ DQS DQS
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Q
Q
Q
Q
Q
Q
Q
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Write to power down entry
T0 CK CK CMD CKE DQ DQS DQS T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4
WR BL=4 WL D D D D tWTR
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Ty
Ty+1
Ty+2
Ty+3
CMD CKE DQ DQS DQS
WR BL=8 WL D D D D D D D D tWTR
Write with Autoprecharge to power down entry
T0 CK CK CMD
WRA BL=4 PRE
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
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CKE DQ
WL D D D D WR*1
DQS DQS T0 CK CK CMD CKE DQ DQS DQS
* 1: WR is programmed through MRS WRA BL=8 WL D D D D D D D D WR*1 PRE
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
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Refresh command to power down entry
T0 CK CK CMD CKE
REF
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CKE can go to low one clock after an Auto-refresh command
Active command to power down entry
CMD CKE
ACT
CKE can go to low one clock after an Active command
Precharge/Precharge all command to power down entry
CMD CKE
PR or PRA
CKE can go to low one clock after a Precharge or Precharge all command
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MRS/EMRS command to power down entry
CMD
MRS or EMRS
CKE
tMRD
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2. 9 Asynchronous CKE Low Event
DRAM requires CKE to be maintained "HIGH" for all valid operations as defined in this data sheet. If CKE asynchronously drops "LOW" during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "HIGH" again. DRAM must be fully re-initialized (steps 4 thru 13) as described in initializaliation sequence. DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tDelay specification
tCK CK# CK CKE tDelay
Stable clocks
CKE asynchronously drops low
Clocks can be turned off after this point
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H5PS1G63EFR Input Clock Frequency Change during Precharge Power Down
DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
Clock Frequency Change in Precharge Power Down Mode
T0 CK CK CMD CKE
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
NOP
NOP
NOP
NOP
DLL RESET
NOP
Valid
Frequency Change Occurs here
200 Clocks
ODT
tRP tAOFD tXP
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2.10 No Operation Command
The No Operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The purpose of the No Operation command (NOP) is to prevent the DDR2 SDRAM from registering any unwanted commands between operations. A No Operation command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
2.11 Deselect Command
The Deselect command performs the same function as a No Operation command. Deselect command occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don't cares.
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3. Truth Tables
3.1 Command truth table.
CKE Function Previous Cycle H H H Current Cycle H H L CS RAS CAS WE BA0 BA1 BA2 BA X X X X A15-A11 A10 A9 - A0 Notes
(Extended) Mode Register Refresh (REF) Self Refresh Entry
L L L H
L L L X H L L L H H H H H X X H X H
L L L X H H H H L L L L H X X H X H
L H H X
OP Code X X X X
1,2 1 1
Self Refresh Exit
L
H L H L L H L L H H H X X
X
X
X
X
1,7
Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto-Precharge No Operation Device Deselect
H H H H H H H H H
H H H H H H H X X
L L L L L L L L H H
BA X BA BA BA BA BA X X
X X
L H Row Address
X X
1,2 1 1,2 1,2,3, 1,2,3, 1,2,3 1,2,3 1 1
Column Column Column Column X X
L H L H X X
Column Column Column Column X X
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H
L L H H X
X
X
X
X
1,4
L
H L H
X
X
X
X
1,4
1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock. 2. Bank addesses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MR BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" in section 1.4 for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in section 1.2.2. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 1.2.2.4. 6. "X" means "H or L (but a defined logic level)". 7. Self refresh exit is asynchronous. 8. VREF must be maintained during Self Refresh operation
Table 6. Command truth table
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3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE Current State 2 Previous Cycle (N-1) L Power Down L L Self Refresh L Bank(s) Active H H All Banks Idle H H L H REFRESH Self Refresh Entry 6, 9, 11,13 7 H L L DESELECT or NOP DESELECT or NOP DESELECT or NOP Self Refresh Exit Active Power Down Entry Precharge Power Down Entry 4, 5,9 4,8,10,11,13 4, 8, 10,11,13 H L DESELECT or NOP X Power Down Exit Maintain Self Refresh 4, 8, 11,13 11, 15
1
Command (N) 3
1
Current Cycle (N) L
Action (N) 3 RAS, CAS, WE, CS X Maintain Power-Down
Notes
11, 13, 15
Refer to the Command Truth Table
Notes:
CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge N. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self Refresh mode can only be entered from the All Banks Idle state. 7. Must be a legal command as defined in the Command Truth Table. 8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. 9. Valid commands for Self Refresh Exit are NOP and DESELECT only. 10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or www..com operations are in progress. See section 2.2.9 "Power Down" and 2.2.8 "Self Refresh Command" for a detailed list of Precharge restrictions. 11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 2.2.2.4. 13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 2.2.7. 14. CKE must be maintained high while the SDRAM is in OCD calibration mode . 15. "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to "1" in EMRS(1) ). 1. 2. 3. 4. 5.
3.3 Data Mask Truth Table
Name (Functional) Write enable Write inhibit DM L H DQs Valid X Note 1 1
1. Used to mask write data, provided coinsident with the corresponding data
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4. Operation Conditions 4.1 Absolute Maximum DC Ratings
Symbol
VDD VDDQ VDDL VIN, VOUT TSTG II IOZ
Parameter
Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on VDDL pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V) Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled
Rating
- 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100 -2 uA ~ 2 uA -5 uA ~ 5 uA
Units
V V V V C uA uA
Notes
1 1 1 1 1, 2
Note:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions. please refer to JESD51-2 standard.
4.2 Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C Notes 1
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. www..com operation temperature range are the temperature which all DRAM specification will be supported. 2. At 0 - 85C, 3. At 85-95C operation temperature range, doubling refresh commands in frequency to a 32ms period (tREFI=3.9us) is required, and to enter to self refresh mode at this temperature range, and EMRS command is required to change internal refresh rate.
4.3 Thermal Characteristics
PARAMETER
TC TJ Theta_JA Theta_JC
Description
Case Temperature Junction Temperature Thermal resistance junction to ambient Thermal resistance junction to case
Value (Ta=25 )
41 43 69.6 6.07
Value (Ta=70 )
86 88 69.6 6.07
UNIT
NOTES
7 7
/W /W
1,2,3,4,5,7 1,2,6,7
1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD-51 standared. 2. Theta_JA and Theta_JC must be measured with the high effective thermal conductivity test board defined in JESD51-7 3. Airflow information must be deocumented for Theta_JA. 4. Theta_JA should only be used for comparing the thermal performance of signle packages and not for system related junction. 5. Theta_JA is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure as described in JESD-51. The environment is sometimes referred to as "still-air" although natural convection causes the air to move. 6. Theta_JC case surface is defined as the "outside surface of the package (case) closest to the chip mounting area when that same surface is properly hear sunk" so as to minimize temperature variation across that surface. 7. Test condition : Voltage 1.8V / Frequency : 400Mhz Rev. 1.1/Oct. 2008 56
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5. AC & DC Operating Conditions
5.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Symbol VDD VDDL VDDQ VREF VTT Note: 1. Min. Typ. and Max. values increase by 100mV for 400Mhz speed option. 2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD. 3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 5. VTT of transmitting device must track VREF of receiving device. Parameter Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V Notes 1 1,2 1,2 3,4 5
5.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION Rtt effective impedance value for EMR(A6,A2)=0,1; 75 ohm Rtt effective impedance value for EMR(A6,A2)=1,0; 150 ohm Rtt effective impedance value for EMR(A6,A2)=1,1; 50 ohm Deviation of VM with respect to VDDQ/2
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SYMBOL Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM
MIN 60 120 40 -6
NOM 75 150 50
MAX 90 180 60 +6
UNITS NOTES ohm ohm ohm % 1 1 1 1
Note : 1. Test condition for Rtt measurements Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL(ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18 VIH (ac) - VIL (ac) I(VIH (ac)) - I(VIL (ac)) Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
Rtt(eff) =
2 x Vm delta VM =( VDDQ - 1) x 100%
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5.2.1 Input DC Logic Level
Symbol VIH(dc) VIL(dc) Parameter dc input logic HIGH dc input logic LOW Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
5.2.2 Input AC Logic Level
Symbol VIH (ac) VIL (ac) Parameter ac input logic HIGH ac input logic LOW Min. VREF + 0.250 Max. VREF - 0.250 Units V V Notes 1 1
Note : 1. 400Mhz at 1.8V supported
5.2.3 AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Note: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the figure below. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
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VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS
VSWING(MAX)
delta TF Falling Slew = VREF - VIL(ac) max delta TF
delta TR
Rising Slew = VIH(ac) min - VREF delta TR
< Figure : AC Input Test Signal Waveform>
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5.2.4 Differential Input AC logic Level
Symbol VID (ac) VIX (ac) Note:
Parameter ac differential input voltage ac differential cross point voltage
Min. 0.5 0.5 * VDDQ - 0.175
Max. VDDQ + 0.6 0.5 * VDDQ + 0.175
Units Notes V V 1 2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC).
VDDQ VTR VID VCP VSSQ
< Differential signal levels >
Note: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is www..com expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
Crossing point
VIX or VOX
5.2.5 Differential AC output parameters
Symbol VOX (ac) Note: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross. Parameter ac differential cross point voltage Min. 0.5 * VDDQ - 0.125 Max. 0.5 * VDDQ + 0.125 Units V Notes 1
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5.3.1 Output AC Test Conditions
Symbol
VOH VOL
Parameter Minimum Required Output Pull-up under AC Test Load Maximum Required Output Pull-down under AC Test Load Output Timing Measurement Reference Level
SSTL_18 Class II
VTT + 0.603 VTT - 0.603
Units
V V
Notes
VOTR Note:
0.5 * VDDQ
V
1
1. The VDDQ of the device under test is referenced.
5.3.2 Output DC Current Drive
Symbol IOH(dc) IOL(dc) Note: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. Parameter Output Minimum Source DC Current Output Minimum Sink DC Current SSTl_18 - 13.4 13.4 Units mA mA Notes 1, 3, 4 2, 3, 4
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5.3.3 OCD default characteristics
Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications ( Toper; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUTVDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4. Slew rate measured from vil(ac) to vih(ac). 5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions. Output Slew rate load:
VTT
Parameter
Min 0 0
Nom -
Max 1.5 4
Unit ohms ohms ohms V/ns
Notes 1 6 1,2,3 1,4,5,6,7,8
Sout
1.5
-
5
25 ohms
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Output (Vout)
Reference point
7. DRAM output slew rate specification applies to 400Mhz speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification.
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5.4 IDD Specifications & Test Conditions IDD Specifications(max)
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5 IDD6 Normal F S 25C 400Mhz 95 120 10 32 45 25 12 55 230 215 170 10 290 20L 500Mhz 105 130 10 35 50 25 12 65 300 250 180 10 300 Units mA mA mA mA mA mA mA mA mA mA mA mA mA
IDD7 (1KB)
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H5PS1G63EFR IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol IDD0 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS min(IDD) ; CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating one bank active-read-precharge ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MR(12) = 0 Slow PDN Exit MR(12) = 1 Units mA
IDD1
mA
IDD2P IDD2Q IDD2N
mA mA mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
mA
IDD4W
mA
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IDD4R
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
IDD6
mA
IDD7
mA
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Note : 1. 2. 3. 4. 5. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V IDD specifications are tested after the device is properly initialized Input slew rate is specified by AC Parametric Test Condition IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMR bits 10 and 11. 6. For 400Mhz testing, tCK in the Conditions should be interpreted as tCK(avg). 7. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
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H5PS1G63EFR IDD Testing Parameters
For purposes of IDD testing, the following parameters are to be utilized. Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRASmin(IDD) tRASmax(IDD) tRP(IDD) tRFC(IDD) 25C 6 15 60 10 2.5 45 70k 15 127.5
20L
7 15 60 10 2 45 70k 15 127.5
Units tCK ns ns ns ns ns ns ns ns
Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA
5.5. Input/Output Capacitance
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400/500Mhz Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Symbol Min CCK CDCK CI CDI CIO CDIO 1.0 x 1.0 x 2.5 x Max 2.0 0.25 1.75 0.25 3.5 0.5 pF pF pF pF pF pF Units
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5.6 Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification for Address and Control Pins A0-A12, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT
Parameter
Maximum peak amplitude allowed for overshoot area (See Figure 1): Maximum peak amplitude allowed for undershoot area (See Figure 1): Maximum overshoot area above VDD (See Figure1). Maximum undershoot area below VSS (See Figure 1).
Specification
0.9V 0.9V 0.45 V-ns 0.45 V-ns
Maximum Amplitude
Overshoot Area
Volts (V)
VDD VSS
Undershoot Area
Maximum Amplitude Time (ns) AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK, CK
Parameter
Maximum peak amplitude allowed for overshoot area (See Figure 2): Maximum peak amplitude allowed for undershoot area (See Figure 2): Maximum overshoot area above VDDQ (See Figure 2). www..com Maximum undershoot area below VSSQ (See Figure 2).
Specification
0.9V 0.9V 0.23 V-ns 0.23 V-ns
Maximum Amplitude
Overshoot Area
Volts (V)
VDDQ VSSQ
Undershoot Area
Maximum Amplitude Time (ns)
Figure 2: AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins
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Power and ground clamps are required on the following input only pins: 1. BA0-BA2 2. A0-A12 3. RAS 4. CAS 5. WE 6. CS 7. ODT 8. CKE V-I Characteristics table for input only pins with clamps Voltage across clamp(V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
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Minimum Power Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0
Minimum Ground Clamp Current (mA) 0 0 0 0 0 0 0 0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
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6. Electrical Characteristics & AC Timing Specification
6.1 Refresh Parameters by Device Density
( TOPER VDDQ = 1.8 +/- 0.1V; VDD = 1.8 +/- 0.1V)
Parameter Refresh to Active/Refresh command time Average periodic refresh interval
Note : 1: If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 2. This is an optional feature. For detailed information, please refer to "operating temperature condition" in this data sheet.
Symbol tRFC 0 tREFI 85 TCASE TCASE 85 95
1Gb 127.5 7.8 3.9
Units Notes ns us us 1 1
6.2 DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed Parameter Bin(CL-tRCD-tRP) CAS Latency tRCD tRP*1 tRAS www..com tRC
Note : * Paramters' value of each speed bin except for 400Mhz is only for the reference data. 1. 8 bank device Precharge All Allowance : tRP for a Precharge All command for an 8 Bank device will equal to tRP+1*tCK, where tRP are the values for a single bank , which are shown in the table above. 2. Refer to Specific Notes 3.
500Mhz min 7-7-7 7 15 15 45 60
400Mhz min 6-6-6 6 15 15 45 60
300Mhz min 5-5-5 5 15 15 45 60
200Mhz min 3-3-3 3 15 15 45 60
100Mhz min 3-2-2 3 20 20 50 60
Units
Note s
tCK ns ns ns ns 2
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6.3 Timing Parameters by Speed grade
Parameter
DQ output access time from CK/CK DQS output access time from CK/CK CK HIGH pulse width CK LOW pulse width CK half period Clock cycle time, CL=x DQ and DM input setup time DQ and DM input hold time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS First DQS latching transition to associated clock edge DQS input HIGH pulse width DQS input LOW pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time
Symbol min
tAC tDQSCK tCH(avg) tCL(avg) tHP tCK(avg) tDS(base) tDH(base) tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRE tWPST tIS(base) tIH(base) tRPRE tRPST tRAS tRRD tFAW tCCD tWR tDAL -350 -300 0.45 0.45
20L max
+350 +300 0.55 0.55 8000 tAC max tAC max tAC max 200 300 + 0.25 0.6 1.1 0.6 70000 -
25C min
-400 -350 0.45 0.45 min(tCL(abs), tCH(abs)) 2500 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 400 400 0.9 0.4 45 10 45 2 15 WR+tnRP -
Unit max
+400 +350 0.55 0.55 8000 tAC max tAC max tAC max 200 300 + 0.25 0.6 1.1 0.6 70000 ps ps tCK(avg) tCK(avg) ps ps ps ps tCK(avg) tCK(avg) ps ps ps ps ps ps tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) ps ps tCK(avg) tCK(avg) ns ns ns nCK ns nCK
Note
min(tCL(abs), tCH(abs)) 2000 50 125 0.6 0.35 tAC min 2*tAC min tHP - tQHS - 0.25 0.35 0.35 0.2 0.2 2 0.35 0.4 300 300 0.9 0.4 45 10 45 2 14 WR+tnRP
6,7,8 6,7,8
18 18 18 13
www..com Write preamble
Write postamble Address and control input setup time Address and control input hold time Read preamble Read postamble Activate to precharge command Active to active command period for 2KB page size products (x16) Four Active Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time
10 5,7,9 5,7,9
3 4
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Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command
Symbol min
tWTR tRTP tXSNR tXSRD 7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC(min) tAC(min) +2 2.5 tAC(min) tAC(min) +2 3 8 0
20L max
-
25C min
7.5 7.5 tRFC + 10 200 2 2 8 - AL 3 2 tAC(max) +0.7 2 tAC(min) tAC(min) +2 2.5 tAC(min) tAC(min) +2 3 8 12 0 tIS+tCK(av) +tIH 12 2 tAC(max) +0.7 2tCK(avg)+ tAC(max)+1 2.5 tAC(max) +0.6 2.5tCK(avg)+ tAC(max)+1 -
Unit max
ns ns ns nCK nCK nCK nCK nCK nCK ns ns nCK ns ns nCK nCK ns ns
Note s
3
Exit precharge power down to any non-read command tXP Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (HIGH and LOW pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Minimum time clocks remains ON after CKE asynchronously drops LOW tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT tDelay
1 1, 2
16 6,16
2tCK(avg)+ tAC(max)+1 2.5 tAC(max) +0.6 2.5tCK(avg)+ tAC(max)+1
17 17
tIS+tCK(av) +tIH
15
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General notes, which may apply for all AC parameters
1. DDR2 SDRAM AC timing reference load The following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DQ DQS DQS RDQS RDQS
DUT
Output Timing reference point 25
VTT = VDDQ/2
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 2. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF www..com + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (+250mV to -500 mV for falling egdes). c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe.
3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown below.
VDDQ DUT
DQ DQS, DQS RDQS, RDQS
Output Test point 25
VTT = VDDQ/2
Slew Rate Test Load
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4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMR "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMR, the complementary pin, DQS, must be tied externally to VSS through a 20 to 10 K resistor to insure proper operation.
DQS
tDQSH
tDQSL
DQS/ DQS
DQS tWPRE VIH(ac) VIH(dc) D VIL(ac) tDS tDS VIH(ac) DMin VIL(ac) tDH DMin D D VIL(dc) tDH DMin VIL(dc) VIH(dc) D tWPST
DQ
DM
DMin
Figure -- Data input (write) timing
tCH CK
tCL
CK/CK
CK
DQS
DQS/DQS
DQS tRPRE tRPST Q tDQSQmax tQH Q Q tDQSQmax tQH Q
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DQ
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions. 6. All voltages referenced to VSS. 7. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
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Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. AL = Additive Latency 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 * tCK or 2 * nCK) is required irrespective of operating frequency 5. Timings are specified with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 6. Timings are guaranteed with DQs, DM, and DQS's(DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 7. Timings are specified with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System Derating for other slew rate values. 8. tDS and tDH derating
tDS, tDH Derating Values for 400Mhz (ALL units in 'ps', Note 1 applies to entire Table) DQS, DQS Differential Slew Rate 4.0 V/ns tDS 2.0 1.5 1.0 DQ 0.9 www..com Slew 0.8 rate 0.7 V/ns 0.6 100 67 0 tDH 45 21 0 3.0 V/ns tDS 100 67 0 -5 tDH 45 21 0 -14 2.0 V/ns tDS 100 67 0 -5 -13 tDH 45 21 0 -14 -31 1.8 V/ns tDS 79 12 7 -1 -10 tDH 33 12 -2 -19 -42 1.6 V/ns tDS 24 19 11 2 -10 tDH 24 10 -7 -30 -59 1.4 V/ns tDS 31 23 14 2 tDH 22 5 -18 -47 1.2 V/ns tDS 35 26 14 tDH 17 -6 -35 1.0 V/ns tDS 38 26 tDH 6 -23
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating value listed in Table x. Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ` VREF(dc) to ac region', use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.) Hold(tDH) nominal slew rate for a rising signal is defined as the slew between the last crossing of Vil(dc) max and the first crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig c.) If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)
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Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
Fig. a. Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
tIS, tDS
tIH, tDH
tIS, tDS
tIH, tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal slew rate
VREF(dc) nominal slew rate VREF to ac region
VIL(dc)max
VIL(ac)max Vss
Delta TF
Setup Slew Rate = Falling Signal VREF(dc)-VIL(ac)max Delta TF
Delta TR
Setup Slew Rate = Rising Signal VIH(ac)min-VREF(dc) Delta TR
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Fig. b. Illustration of tangent line for tIS,tDS
CK, DQS
CK, DQS
tIS, tDS
VDDQ
tIH, tDH
nominal line
tIS, tDS
tIH, tDH
VIH(ac)min
VIH(dc)min tangent line VREF(dc) Tangent line VIL(dc)max VREF to ac region VIL(ac)max Nomial line Vss Delta TF
Delta TR
Setup Slew Rate Tangent line[VIH(ac)min-VREF(dc)] = Rising Signal Delta TR
Setup Slew Rate Tangent line[VREF(dc)-VIL(ac)max] = Falling Signal Delta TF
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Fig. c. Illustration of nominal line for tIH, tDH
CK, DQS
CK, DQS
tIS, tDS
VDDQ
tIH, tDH
tIS, tDS
tIH, tDH
VIH(ac)min
VIH(dc)min
dc to VREF region
VREF(dc)
nominal slew rate nominal slew rate
VIL(dc)max
VIL(ac)max
Vss Delta TR
Delta TF
Hold Slew Rate = Rising Signal
VREF(dc)-VIL(dc)max Delta TR
VIH(dc)min - VREF(dc) Hold Slew Rate = Falling Signal Delta TF
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Fig. d. Illustration of tangent line for tIH , tDH
CK, DQS
CK, DQS
tIS, tDS
VDDQ
tIH, tDH
tIS, tDS
tIH, tDH
VIH(ac)min
nominal line
VIH(dc)min tangent line VREF(dc)
dc to VREF region
VIL(dc)max
Tangent line
nominal line
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max] = Rising Signal Delta TR
Tangent line[VIH(ac)min-VREF(dc)] Hold Slew Rate = Falling Signal Delta TF
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9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values for 400Mhz CK, CK Differential Slew Rate 2.0 V/ns tIS
4.0 3.5 3.0 2.5 2.0 1.5 1.0 +15 +143 +133 +120 +100 +67 0 -5 -13 -22 -34 -60 -100 -168 -200 -325 -517 -1000
1.5 V/ns tIH tIS
+180 +173 +163 +150 +130 +97 +30 +25 +17 +8 -4 -30 -70 -138 -170 -395 -487 -970
1.0 V/ns tIH tIS
+210 +203 +193 +180 +150 +127 +60 +55 +47 +38 +26 0 -40 -108 -140 -265 -457 -940
tIH
+154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125
+124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095
Command / 0.8 Address Slew 0.7 rate(V/ns) 0.6
0.5 0.4 0.3 0.25 0.2 0.15 0.1
0.9
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value to the derating value listed in above Table.
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Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate for line between shaded `VREF(dc) to ac region', use nominal slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(dc) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc). If the actual is always later than the nominal slew rate line between shaded `dc to VREF(dc) region', use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(dc) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.) Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization.
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10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( t CL, t CH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces. 12. t QH = t HP - t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH,tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any given cycle. 14. t DAL = (nWR) + ( tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR refers to the t WR parameter stored in the MR.
15. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down. 16. ODT turn www..com on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistenet.
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7. Package Dimension(x16)
84Ball Fine Pitch Ball Grid Array Outline
8.00 0.10
A1 BALL MARK
13.00 0.10
< Top View>
< SIDE View>
0.15
0.05
2-R0.13MAX
0.80 X 8 = 6.40
987 321
1.10
2.10 0.10 A1 BALL MARK
0.10 0.05
0.34
A B C D E F G H J K L M N P R
84X
0.45
0.05
1.60 1.60
0.80
< Bottom View>
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0.80

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